Chisel-HDL-Guide

This repository is a Traditional Chinese tutorial guide for Chisel, a hardware description language used to design digital circuits. Unlike software programming languages that run on a computer, Chisel is used to describe the logic of chips and other hardware. The guide is written for readers who already understand basic digital logic but have not used Scala, the programming language that Chisel is built on.

The content spans 14 chapters and roughly 4,300 lines of text, covering everything from basic circuit constructs to building a full chip-on-a-chip generator in the style used by the Chipyard research project at Berkeley. The chapters progress through types and registers, arithmetic logic units, state machines, handshake-based communication interfaces, generator patterns, simple processor pipelines, memory and clock domain handling, formal verification basics, and advanced interconnect frameworks called Diplomacy and TileLink.

The repository also contains a set of example projects that implement the circuit modules described in the guide. These examples compile and run through simulation using a tool called Verilator, and all nine included tests pass. The examples cover a range of circuits including counters, a register file, a queue, and a simple processor called Wildcat. A single command can generate SystemVerilog output for ten top-level modules.

The guide uses ChiselSim as its testing framework, which is the current official approach, and explicitly notes that the older ChiselTest framework has been deprecated. The guide targets Chisel version 7.13.0 with Scala 2.13.18. Running the examples requires a Java development kit and the sbt build tool; simulation additionally requires Verilator.

The written content is credited as an original derivative of Martin Schoeberl's book "Digital Design with Chisel" and the official Chisel documentation. Code is released under the MIT license.