DAE-Pipeline-CPU
An small in-order, decoupled frontend-backend, pipeline CPU which implements RV32I_Zicsr and boots FreeRTOS.
An educational RISC-V processor design in SystemVerilog for teaching how real CPUs work, with simulation via Verilator, 58 standard test programs, a FreeRTOS demo, and instructor documentation.
DAE Pipeline CPU is an educational processor design written to help students and instructors understand how a real CPU works at the hardware level. It implements the RV32I instruction set, which is a minimal, open-standard set of processor instructions defined by the RISC-V project, plus a small extension for control and status registers used in handling interrupts and traps. The design is intentionally small and readable rather than fast, making it useful for studying and teaching.
The processor splits its work into two halves called the frontend and the backend. The frontend fetches instructions from memory and decodes them, then places them into a queue. The backend pulls from that queue, checks whether the data each instruction needs is ready (using a component called a scoreboard), runs the actual computation, accesses memory if needed, and writes results back to the register file. Separating the two halves with a queue is a structural idea that appears in more sophisticated processors and is one of the things this design is intended to illustrate.
The project is built with SystemVerilog, which is a hardware description language used to specify digital circuits. To test it, you compile the design using Verilator, a tool that converts SystemVerilog into a C++ simulation that runs on a normal computer. A suite of 58 standard RISC-V test programs runs against the simulated processor, covering both user-level and machine-level instructions. The repository also includes a FreeRTOS demo, showing the processor booting a small real-time operating system kernel, which demonstrates that the design handles interrupts and scheduling correctly.
The repository includes several documentation files that explain the architecture, describe why the design is structured differently from a classic five-stage textbook pipeline, and provide a suggested teaching sequence for instructors. Known limitations are listed explicitly: there is no reorder buffer, no branch prediction beyond assuming branches are not taken, and no cache hierarchy. The authors describe these as deliberate teaching opportunities rather than oversights.
Where it fits
- Run the 58 included RISC-V test programs against the simulated CPU to study how instructions execute in hardware.
- Follow the provided teaching sequence to explain pipelined processor design to computer architecture students.
- Boot the FreeRTOS demo on the simulation to observe how the CPU handles interrupts and operating system scheduling.
- Use the documented architecture as a starting point for adding features like branch prediction or a cache hierarchy.