Verilog-SV-SVA-Guide

Verilog-SV-SVA-Guide is a written learning resource for engineers who design digital hardware circuits. Verilog and SystemVerilog are programming languages used not to write software, but to describe the behavior and structure of hardware such as chips and digital circuits. This guide focuses on the designer's perspective, meaning the person responsible for defining what the hardware should do, rather than the person writing tests to verify it.

The guide is organized into three parts. The first covers Verilog, the foundational language for describing hardware logic including modules, data types, state machines, and the specific coding patterns that translate correctly into actual hardware. The second part covers SystemVerilog, a more modern extension of Verilog that adds features making hardware descriptions clearer and less prone to mistakes. The third and deepest part covers SystemVerilog Assertions, a way of writing formal statements about what a piece of hardware is guaranteed to always do or never do. The guide treats these assertions as a core part of the designer's job, not just a testing afterthought.

The guide explicitly excludes testbench construction, verification methodology frameworks, and class-based randomization, pointing readers to other resources for those topics. The focus stays on design intent and how to express it in machine-checkable form.

Content is available in both English and Traditional Chinese, with the same chapter structure mirrored in both languages. Code examples throughout are short illustrative snippets rather than complete runnable projects. Each chapter follows a consistent structure moving from objectives through concepts, examples, pitfalls, and a summary.

The material is still in progress at time of writing. A content status file tracks which chapters are complete. The guide is released under the MIT license.