Babel
AI-native Chiplet design flow based on open-source EDA toolchain
Babel automates chip design from plain-language requirements through a five-stage AI agent pipeline, using free open-source tools to produce a physical chip layout without expensive commercial software.
Babel is a project that aims to automate chip design using AI agents and open-source tools. Designing a computer chip traditionally requires years of specialist training and expensive commercial software. Babel tries to reduce that barrier by breaking the design process into stages and assigning an AI agent to handle each one, with the agents handing off work to each other through a structured pipeline.
The pipeline has five stages: architecture (deciding what the chip should do and how it is structured), RTL generation (writing the hardware description code in SystemVerilog, a language for specifying digital circuits), verification (running simulations to confirm the design behaves correctly), synthesis (converting the hardware description into a logical netlist), and physical design (placing and routing that netlist into a layout that can be sent to a fabrication process). Each stage uses a different AI agent triggered by a slash command in Claude Code. If a stage fails quality checks, it automatically sends the problem back to an earlier agent to fix.
All the underlying tools are open-source: Yosys handles synthesis, Verilator runs simulations, Magic handles layout and design rule checks, OpenSTA checks timing, and KLayout exports the final layout file. The target fabrication process is ASAP7, a publicly available model of a 7-nanometer chip process developed by Arizona State University. It is a research-grade process, not a commercial one, but it allows realistic chip design practice without proprietary tool licenses.
To start a design, a user describes what they want in plain language, such as a UART controller running at a certain speed, and the architect agent produces a requirement document, an architecture description, and a micro-architecture specification. Subsequent agents work from that specification. The repository's README is written almost entirely in Chinese, so users not reading Chinese will need translation to follow the detailed instructions. The project is in early public development with limited documentation in other languages.
Where it fits
- Design a custom chip by describing what you want in plain language and letting AI agents generate the hardware code through architecture, RTL, and synthesis stages.
- Practice realistic chip design on the ASAP7 7nm process model without purchasing any proprietary EDA tool licenses.
- Run automated verification and simulation on SystemVerilog hardware descriptions using Verilator and open-source tools.
- Prototype digital circuits like UART controllers or ALUs with AI-guided feedback when quality checks fail.