Chips-2.0
Python
★ 0
updated 8y ago
⑂ fork
FPGA Design Suite based on C to Verilog design flow.
No plain-English explanation yet — one is being written right now. Check back in a minute.
gitmyhub
gitmyhub
FPGA Design Suite based on C to Verilog design flow.
No plain-English explanation yet — one is being written right now. Check back in a minute.