Michael Gielda

A List of Free and Open Source Hardware Verification Tools and Frameworks

Project Sparrow: KataOS

The HTML Presentation Framework

RIOT - The friendly OS for IoT

A static website generator - Toss some content, templates, and media in a pan and fry it up!

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Run multiple commands in parallel

Python API to Unified Coverage Interoperability Standard (UCIS) Data

RISC-V Directed Test Framework and Compliance Suite, RiESCUE

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

This repository stores meetings minutes for the SPDX project

An updated and improved Chrome and Firefox extension of the old google chrome extension "Tab Manager".

Typer, build great CLIs. Easy to code. Based on Python type hints.

🪁 A curated list of awesome projects and resources for the Zephyr RTOS project.

Easily turn your Click CLI into a powerful terminal application

This rust compiler backend emmits valid CLR IR, enabling you to use Rust in .NET projects

Serial communication link bit error rate tester simulator, written in Python.

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An extended commonmark compliant parser, with bridges to docutils/sphinx

List of awesome open source hardware tools

A modular build system for hardware

excalidraw with collaboration feature, one-click deploy

A utility allowing you to add comments etc. on top of a website

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Wavious DDR (WDDR) Physical interface (PHY) Hardware

A UI component explorere desiged specifically for Svelte Kit, not spooky

Gmail, Gnus and GPG

Antmicro's open hardware baseboard for the NVIDIA Jetson Nano

One second to read GitHub code with VS Code.

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Import Assertions in Astro

A markdown-it plugin for implementing docutils style roles/directives.

Wavious DDR (WDDR) Physical interface (PHY) Software

Wavious RTOS Base Software

Repository with infrastructure required to build Wavious Software

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Educational materials for RISC-V

AI-ML-NLP Task Group

System Verilog 2017 Pre-processor, Parser, UHDM Compiler. Provides IEEE Design/TB VPI and Python AST API.

CHIPS Alliance Technical Steering Committee

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Peer-to-peer shared types

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Plac: Parsing the Command Line the Easy Way

Font Awesome split to individual SVG and PNG files of different sizes along with Node.JS based generator

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Mapbox GL 3D extrusion demo

Provides DFS ROS example for Snapdragon Flight

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Chisel 3

Examples designs for showing different ways to use SymbiFlow toolchains.

Documentation for SymbiFlow

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UVM 1.2 port to Python

Jupyter notebooks for Renode

Gmail CLI client.

Generic functional policy engine for functional simulation of security policies.

BSP layer for Nvidia Tegra

Contains release packages for Quicklogic FPGA toolchain

The J-Core Jx Platform board hardware.

PolarFire SoC yocto Board Support Package

An abstraction library for interfacing EDA tools

Python module containing system_verilog files for cv32e40p cpu (for use with LiteX).

A collection of demos for Yjs v13 (in beta)

Sphinx extension for displaying console and other sessions.

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

Triple Modular Redundancy

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TF Lite demo on LiteX/VexRiscv soft RISC-V SoC on a Digilent Arty board

PlatformIO Documentation

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A directory of Western Digital’s RISC-V SweRV Cores

TorizonCore repo manifest

Stylish, intuitive and user-friendly prompts.

Internal tests, do not use this!

Dockerfiles for creating build environment for building RIOT projects.

Linux on LiteX-VexRiscv

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Renode - virtual development framework for complex embedded systems

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AXIOM Beta Software

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Verilog to Routing -- Open Source CAD Flow for FPGA Research

SymbiFlow Website Source

A parser for Gina Trapani's todo.txt format with optional extended features

Unfancy JavaScript

A web-based GUI to manage a Todo.txt file

VHDL/Verilog/SystemC code generator, simulator writen in python/c++

PoC of testing Zephyr in Renode

Weekly RISC-V Newsletter

Documenting the Xilinx 7-series bit-stream format.

An Open Source Machine Learning Framework for Everyone

Structure View for ATOM editor, just like Outline view in Eclipse or Structure tool window in IDEA / WebStorm, provides quick navigation for symbols of source code with a tree view.

This repository provides a Linux kernel bootable on RISC-V boards from SiFive

A FPGA friendly 32 bit RISC-V CPU implementation

Render AsciiDoc documents from Gists, GitHub, DropBox and other remote sources in the browser.

System functions and example code for programming the "Blue Pill" STM32-compatible micro-controller boards.

A high performance and small footprint system-on-chip based on Migen

Clize: Turn Python functions into command-line interfaces

Open CASCADE Community Edition: patches/improvements/experiments contributed by users over the official Open CASCADE library.

Awesome IoT. A collaborative list of great resources about IoT Framework, Library, OS, Platform

A browser based code editor

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Open source simulator based on Unreal Engine for autonomous vehicles from Microsoft AI & Research

Zephyr port to riscv architecture

Pure JavaScript reStructuredText parser

EspoCRM Contributors License Agreements

Pythonic task management & command execution.

A curated list of awesome things related to Vue.js

Android installation instructions and default.xml file for Enclustra's Mars-ZX3 Zynq Module

Documentation for RISC-V

RFCs for RISC-V Enhancements and Extensions

The missing prompt function for Node.js

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livereload server in python

Documentation for EspoCRM

Open source software to collaborate on code. Follow us on twitter @gitlabhq

transform restructuredtext documents to html5 + twitter's bootstrap css, deck.js or reveal.js

markdownReader is a extention for chrome, used for reading markdown file.