11-day current streak·26-day longest streak
-
rocket-chip ★ PINNED ⑂
Rocket Chip Generator
Scala ★ 0 5y agoExplain → -
t1-micro58ae ★ PINNED ▣
No description.
SystemVerilog ★ 16 10mo agoExplain → -
arithmetic
No description.
Nix ★ 37 1y agoExplain → -
rocket
A modern version of Rocket Core.
Scala ★ 11 3y agoExplain → -
asl
MLIR Compiler for Arm Specification Lanuage
C++ ★ 7 6mo agoExplain → -
riscv-cosim
No description.
Verilog ★ 7 2y agoExplain → -
diplomatictester
VIP library for you TileLink IP
Scala ★ 7 6y agoExplain → -
rocket-doc
No description.
Scala ★ 7 4y agoExplain → -
chiselmodel
This is a experimental library interacting Chisel based design to foreign language with DPI, to inject arbitrary software model to Chisel and simulate together.
Scala ★ 6 5y agoExplain → -
tilelink
No description.
Scala ★ 5 2y agoExplain → -
SoC
No description.
Scala ★ 4 5y agoExplain → -
firesim-hw
No description.
Scala ★ 3 2y agoExplain → -
rocket-test
RISC-V Core Test Framework
★ 3 3y agoExplain → -
chisel-circt-binder
The Chisel Convert Phase implemented with JVM Panama
Scala ★ 3 2y agoExplain → -
diplomacy
Standalone implementation to diplomacy.(WIP)
Scala ★ 3 4y agoExplain → -
rvv-mlir
The missing Dialect of MLIR on RISC-V Vector
C++ ★ 2 7mo agoExplain → -
firesim ⑂
FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud
★ 2 3y agoExplain → -
ventus-gpgpu ⑂
GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
Scala ★ 2 1y agoExplain → -
circt ⑂
Circuit IR Compilers and Tools
★ 2 1y agoExplain → -
PLCT-Weekly ⑂
软件所PLCT实验室在开源领域的不定期简报
HTML ★ 2 2y agoExplain → -
clx
TL Serdes
Scala ★ 2 3y agoExplain → -
vocotype-cli ⑂
VocoType 是一款运行在本地端侧的隐私安全语音输入工具，通过快捷键即可将语音实时转换为文字并自动输入到当前应用。支持语音转文字MCP、AI 优化文本、自定义替换词典、录音视频转文字等功能，让语音输入更高效、更安全。
★ 1 4mo agoExplain → -
firesim-sw
No description.
C++ ★ 1 2y agoExplain → -
maltese-smt ⑂
A scala SMT library focused on arrays, bitvectors and uninterpreted functions.
★ 1 4y agoExplain → -
nixos-apple-silicon ⑂
Resources to install NixOS bare metal on Apple Silicon Macs
Nix ★ 1 2y agoExplain → -
zvma
No description.
Scala ★ 1 1y agoExplain → -
riscv-boom ⑂
BOOM: Berkeley Out-of-Order Machine
Scala ★ 1 3y agoExplain → -
chipyard ⑂
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
★ 1 3y agoExplain → -
hwacha ⑂
Microarchitecture implementation of the decoupled vector-fetch accelerator
★ 1 3y agoExplain → -
llvm-project ⑂
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.
LLVM ★ 1 1y agoExplain → -
gitakc
No description.
Scala ★ 1 4y agoExplain → -
t1-DRAMsim3 ⑂
DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator
C++ ★ 1 2y agoExplain → -
chisel-panama-standalone-plugin
No description.
C++ ★ 1 2y agoExplain → -
tlaurora
No description.
Scala ★ 1 3y agoExplain → -
rustminer
No description.
Rust ★ 1 7y agoExplain → -
regmapper
No description.
Scala ★ 1 3y agoExplain → -
riscv-debug-spec-ci
No description.
TeX ★ 1 4y agoExplain → -
block-inclusivecache-sifive ⑂
No description.
★ 1 4y agoExplain → -
wishbone
No description.
Scala ★ 1 4y agoExplain → -
cde
A fork version from https://github.com/chipsalliance/api-config-chipsalliance with full git history, documentation and tests.
Scala ★ 1 5y agoExplain → -
xilinx
No description.
Scala ★ 1 5y agoExplain → -
gitmirror
No description.
Scala ★ 1 5y agoExplain → -
berkeley-hardfloat ⑂
No description.
★ 1 2y agoExplain → -
CalculatePhysicExercise
Homework
FORTRAN ★ 1 10y agoExplain → -
sn-bindgen ⑂
Scala 3 native binding generator + libclang facade
Scala ★ 0 6mo agoExplain → -
mlir-www ⑂
No description.
★ 0 10mo agoExplain → -
herdtools7 ⑂
The Herd toolsuite to deal with .cat memory models (version 7.xx)
★ 0 11mo agoExplain → -
espresso ⑂
No description.
★ 0 1y agoExplain → -
om-bug ▣
No description.
Nix ★ 0 1y agoExplain → -
riscv-v-spec ⑂
Working draft of the proposed RISC-V V vector extension
★ 0 3y agoExplain → -
dwbb-impl
No description.
Nix ★ 0 1y agoExplain → -
felix-infra ⑂
The entry point of Felix Universe.
★ 0 4y agoExplain → -
riscv-isa-manual ⑂
RISC-V Instruction Set Manual
★ 0 1y agoExplain → -
scalehls ⑂
A scalable High-Level Synthesis framework on MLIR
★ 0 4y agoExplain → -
ha-core ⑂
:house_with_garden: Open source home automation that puts local control and privacy first.
★ 0 2y agoExplain → -
tvip-axi ⑂
AMBA AXI VIP
★ 0 2y agoExplain → -
ide-dbg
No description.
Scala ★ 0 2y agoExplain → -
mill ⑂
Your shiny new Java/Scala build tool!
★ 0 2y agoExplain → -
nixpkgs ⑂
Nix Packages collection
Nix ★ 0 1y agoExplain → -
utils
No description.
Scala ★ 0 3y agoExplain → -
tsc ⑂
CHIPS Alliance Technical Steering Committee
★ 0 3y agoExplain → -
autoclonetype2_bug ▣
No description.
Scala ★ 0 5y agoExplain → -
test
No description.
★ 0 3y agoExplain → -
firrtl-spec ⑂
The specification for the FIRRTL language
★ 0 3y agoExplain → -
verilator ⑂
Verilator open-source SystemVerilog simulator and lint system
★ 0 3y agoExplain → -
gecko-dev ⑂
Read-only Git mirror of the Mercurial gecko repositories at https://hg.mozilla.org. How to contribute: https://firefox-source-docs.mozilla.org/contributing/contribution_quickref.html
★ 0 3y agoExplain → -
riscv-opcodes ⑂
RISC-V Opcodes
Python ★ 0 2y agoExplain → -
musl
No description.
C ★ 0 3y agoExplain → -
riscv-debug-spec ⑂
Working Draft of the RISC-V Debug Specification Standard
TeX ★ 0 4y agoExplain → -
ara ⑂
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core
C ★ 0 4y agoExplain → -
sifive-blocks ⑂
Common RTL blocks used in SiFive's projects
★ 0 4y agoExplain → -
ibex-wrapper ⑂
Wrapper for lowRISC Ibex
★ 0 4y agoExplain → -
cva6-wrapper ⑂
Wrapper for ETH Ariane Core
★ 0 4y agoExplain → -
Modular-Multiplication
No description.
★ 0 4y agoExplain → -
repo ⑂
Arch Linux CN Repository
Shell ★ 0 4y agoExplain → -
sha3 ⑂
No description.
★ 0 4y agoExplain → -
chisel-circt ⑂
Library to compile Chisel circuits using LLVM/MLIR (CIRCT)
★ 0 4y agoExplain → -
chiselv ⑂
A RISC-V Core (RV32I) written in Chisel HDL
★ 0 4y agoExplain → -
riscv-bitmanip ⑂
Working draft of the proposed RISC-V Bitmanipulation extension
★ 0 4y agoExplain → -
rocket-dsp-utils ⑂
Tools for integrating DspTools components into a rocket-chip
★ 0 3y agoExplain → -
icenet ⑂
Network components (NIC, Switch) for FireBox
★ 0 4y agoExplain → -
mithril ⑂
Pure Rust Monero Miner
★ 0 4y agoExplain → -
f2qr
No description.
Scala ★ 0 6y agoExplain → -
fudian ⑂
Open source high performance IEEE-754 floating unit
Scala ★ 0 4y agoExplain → -
api-config-chipsalliance ⑂
A Scala library for Context-Dependent Evironments
Scala ★ 0 4y agoExplain → -
barstools ⑂
Useful utilities for BAR projects
Scala ★ 0 4y agoExplain → -
XiangShan ⑂
Open-source high-performance RISC-V processor
★ 0 4y agoExplain → -
rc_topname_bug
No description.
Scala ★ 0 5y agoExplain → -
riscv-sodor ⑂
educational microarchitectures for risc-v isa
★ 0 4y agoExplain → -
testchipip ⑂
No description.
Scala ★ 0 4y agoExplain → -
dsptools ⑂
A Library of Chisel3 Tools for Digital Signal Processing
★ 0 3y agoExplain → -
automaton
No description.
Scala ★ 0 5y agoExplain → -
utility
No description.
Scala ★ 0 5y agoExplain → -
chisel3 ⑂
Chisel 3
Scala ★ 0 4y agoExplain → -
firrtl ⑂
Flexible Intermediate Representation for RTL
Scala ★ 0 5y agoExplain → -
gemmini ⑂
Berkeley's Systolic Array Generator
★ 0 4y agoExplain → -
copris
Fork from http://bach.istc.kobe-u.ac.jp/copris
Java ★ 0 6y agoExplain → -
chisel-testers ⑂
Provides various testers for chisel users
Scala ★ 0 4y agoExplain → -
fpga-shells ⑂
No description.
Scala ★ 0 4y agoExplain →
No repos match these filters.