Wilson Snyder

Verilator open-source SystemVerilog simulator and lint system

Test suite designed to check compliance with the SystemVerilog standard.

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

SweRV EH1 core

The MyHDL development repository

A simple opinionated yaml formatter that keeps your comments!

Icarus Verilog

A simple, basic, formally verified UART controller

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Conda build recipes for the toolchains needed by LiteX / MiSoC firmware

A formatter for reStructuredText

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

HW Design Collateral for Caliptra RoT IP

RTLMeter benchmark suite

Extended and external tests for Verilator testing

A massively parallelized gcov wrapper

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

No description.

A mini-tutorial / cheatsheet / link-collection to get you started documenting Python code using Sphinx.

No description.