11-day longest streak
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TraceWeave ★ PINNED
简洁的测试平台日志,波形(FSDB/VCD),根因分析MCP Server. A Simple and Universal MCP Server to Debug Testbench Simulation Failures Via Log Parsing And Waveform Analysis (FSDB/VCD)
Python ★ 61 3d agoExplain → -
awesome-formal-verification-skill ★ PINNED
面向 AI 编程 Agent 的开源形式验证技能库,聚焦 FPV、SVA、证明优化、TCL 脚本与可扩展的形式验证工作流。Open-source formal verification skills for AI coding agents, focused on FPV, SVA, proof optimization, TCL scripting, and scalable verification workflows.
SystemVerilog ★ 23 5d agoExplain → -
liandan ★ PINNED
面向 Codex 与 Claude 的可审计知识蒸馏工具,将 Office、PDF 和 Markdown 转化为结构化文档、可复用知识模块或可发布的 Skill。Auditable knowledge distillation for Codex and Claude—turn Office files, PDFs, and Markdown into structured docs, reusable knowledge modules, or production-ready Skills.
Python ★ 0 18d agoExplain → -
gen-tb-skill ★ PINNED
Claude Code / Codex CLI skill that scaffolds a runnable UVM testbench (APB / AHB-Lite / AXI4-Lite + generic-bus fallback) from an IP spec and register table, with a UVM-sequence flow for DV and a tb_api:: task BFM for DE. | 基于 IP 规格书与寄存器表一键生成可运行的 UVM 验证环境,内建 APB / AHB-Lite / AXI4-Lite,其它单通道总线走 generic 回退,同时为 DV 提供 UVM 序列接口、为 DE 提供 tb_api:: 任务
Python ★ 20 18d agoExplain → -
cov-hunter
覆盖率空洞分析全闭环工具,用于生成自然语言描述覆盖率报告,根据报告生成直接用例,并评判此用例覆盖率数据命中情况。A comprehensive, closed-loop tool for coverage gap analysis that generates natural-language coverage reports, automatically generates direct cases, and evaluates the coverage hit status of the generated test cases.
Python ★ 10 29d agoExplain → -
take-root
CLI harness Agent:6 个 persona 协作,把想法推进到计划、实现和测试闭环. CLI Harness Agent: 6 Personas Collaborating to Drive Ideas Through a Closed Loop of Planning, Implementation, and Testing
Python ★ 9 2mo agoExplain → -
AI_Formal_Counter
jaspergold fpv counter abstruction skills
SystemVerilog ★ 5 2mo agoExplain → -
jasper-lint-agent
No description.
Python ★ 4 4mo agoExplain → -
spi_verification
No description.
SystemVerilog ★ 4 5mo agoExplain → -
vcs-verification-of-apb-based-uart-master-core
No description.
SystemVerilog ★ 1 3mo agoExplain → -
verification-of-apb-based-uart-master-core ⑂
UVM-based functional verification of an APB-based UART Master Core RTL. Includes multi-agent environment, assertions, coverage collection, and multiple test scenarios (full/half duplex, parity, framing, timeout errors) achieving 100% functional coverage and protocol compliance.
★ 0 9mo agoExplain → -
opentitan ⑂
OpenTitan: Open source silicon root of trust
★ 0 3mo agoExplain → -
openclaw ⑂
Your own personal AI assistant. Any OS. Any Platform. The lobster way. 🦞
★ 0 4mo agoExplain → -
SVA-Local-Variables-Practical-Examples
No description.
SystemVerilog ★ 0 3y agoExplain →
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