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A vLLM patch + hand‑written SM120 SASS kernels: 2‑bit MoE experts + an FP4 "delta" cache that recovers precision — matching the official (NV)FP4 checkpoint's quality on consumer Blackwell cards

27B at 256k context on one RTX 5090 — FP6 + 4-bit KV + MTP spec-decode, hand-written SM120 tensor-core kernels, OpenAI API.

Open-source SM120 (Blackwell) SASS assembler — encode, schedule & assemble GPU machine code, including all tensor-core instructions.

Surgical uncensoring of large language models via Optimal Transport activation hooks

PCIe P2P on consumer RTX 5090 via one GSP firmware registry key — no driver patches.

Reverse-engineered instruction set architecture database for NVIDIA SM120 (Blackwell) GPUs.

Mercury — LD_PRELOAD that unlocks ptxas's 949 internal scheduling knobs.

A high-throughput and memory-efficient inference and serving engine for LLMs

FlashAttention BF16/FP8 for NVIDIA SM120 — per-warp HMMA + QMMA.SF block-scaled, no TMA/TMEM required. Port of MiniMax MSA.

SM120 SASS assembler toolkit

Fork of aztec-packages containing bb_rs to create bindings to Barretenberg