duck-rtl

Duck RTL is a tool that helps AI coding agents write and check hardware description code called Verilog, which is used to design digital chips and circuits. Writing this kind of code is easy for an AI model to get subtly wrong, so Duck RTL wraps the process in a series of automatic checks instead of trusting the model's judgment at each step.

The workflow starts with the agent writing a reference model in Python describing how a piece of hardware should behave, then writing the actual Verilog for it. Duck RTL runs a syntax check on that Verilog, then runs a simulation test using a testing framework called cocotb to compare the Verilog's behavior against the Python reference. If a module has internal states that change over time, called a state machine, Duck RTL can also extract that state machine from the code and turn it into a diagram, without the model having to describe the structure from memory.

The README stresses that every one of these checks is a deterministic tool, not a guess by the AI model, which is why even a smaller and cheaper model can work through the whole process reliably. As proof, the author says a minimal GPU design was built and verified using Claude's lowest cost model tier through this same loop.

It installs as a plugin for Claude Code with two new commands: one that runs the full write, check, and verify loop, and one that turns a Verilog file into a diagram of its state machine. It can also run outside Claude Code as a plain command line tool for other coding agents, as long as Python and a couple of external hardware tools, Icarus Verilog and Graphviz, are installed on the system.

The README lays out a strict order of operations: define the module structure first, then for each module write the reference model, write the Verilog, run the syntax check, then run the simulation, and only after that extract and check the state machine if the module needs one.