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Taito Kick And Run for MiSTer FPGA

BankPanic FPGA core for MiSTer

No description.

Express Raider - MiSTer FPGA core

RX-78 core for MiSTer FPGA

Q*Bert core for MiSTer

A boilerplate for my TIC-80 projects

No description.

A Löve file picker

Fujitsu FM-7

Sharp SM510 in Verilog

A one page CPU in MyHDL

A basic unicode VCD viewer in Python

A Verilog implementation of the Nec uCom-43 4-bit microcontroller from 1978.

A gameboy emulator

Hitachi MB-6885

A script parser in Python that uses Radiant Voices to compile to Sunvox

No description.

A snapshot of 99-bottles-of-beer.net

No description.

CoCo2

MiSTer Port of Game and Watch Games

HDL simulator for LUA

a test for converting jedutil files to verilog

No description.

MiSTer Port of Tomy Scramble Game

No description.

Jaleco Chameleon core for MiSTer FPGA

Matra-Hachette Alice MC-10 for MiSTer FPGA

Another LÖVE ECS

Verilog conversion of the 65C816 VHDL core

Port of the Tatung Einstein for MiSTer FPGA

MAME

Port of Watara Supervision for MiSTer

A VGA driver in Verilog

LoveDebug - A whole new way of debugging your game

Appoooh core

No description.

No description.

A basic disassembler for the NEC μPD77x microcontroller family

Javascript int vectors

non official image for building TIC-80 for Android

This is a port of V'Ball for MiSTer FPGA

DEC-T11 CPU

sn76489an compatible Verilog core, with emphasis on FPGA implementation and Megadrive/Master System compatibility

No description.

Hitachi HD38800

UART in Verilog

Testing the boilerplate

A basic proof of concept for a new data transformation language

DockerFile

Testing Flask, Pandas <= socket.io => Webix. Created on my phone with Termux.