Xiongfei(Alex) GUO

A pure Lua (at least for now) Actor Model framework.

Porting OpenWrt to RISC-V - please check https://github.com/xfguo/riscv-openwrt-port for full instructions.

Generate testbench for your verilog module.

libubox from OpenWrt.

飞思卡尔智能车竞赛源代码(含记忆算法)

No description.

RISC-V OpenWrt Port

SPI Master Core clone from OpenCores

GPIO IP core from opencores.

Wishbone Verification IP

skyeye git repo clone, some modify maybe

A libre implementation of FPGA. Written by chisel.

a clone of "nirgam", some of my modification & improvement.

mirror of usbip on sf.net

ethmac on opencores.org

minsoc opencores.org svn mirror

pysnmp with gevent adapter (developing)

Openwrt favorite linux kernel version. (4.1.16)

No description.

generic_fifos from OpenCores/ASICS.ws

Wishbone Multi-Ports Memory Slave Module

10/100/1000 Mbps Tri-Mode Ethernet MAC clone from OpenCores.org

JTAG Test Access Port from OpenCores

Advanced Debug System by Nathan Yawn clone from OpenCores.org

Key-Value Database for SPI NOR Flash

Wishbone Memory IP Library

Wishbone Interconnect Library

OR1200 OpenRISC processor

No description.

A Lua C-extension for daemonizing a process.

vlsi class project in Fudan Univ.

TCP/IP controlled VPI JTAG Interface.

Rocket Chip Generator

《Trello: 小团队项目管理的利器》Slide

Submit Resume, Filling out Questionnaire.

Abstraction for pysnmp

No description.

RT-Thread is an open source real-time operating system for embedded devices from China.

downloadsplugin for trac

dockutils for my Thinkpad X200

Torch installation in a self-contained folder

The official git repository for Contiki, the open source OS for the Internet of Things

Cerbero build system used to build the official upstream GStreamer 1.0 SDK binaries

No description.

mirror of http://code.google.com/p/menuconfig/, menuconfig is a easier way to configure your project.

Fork of OpenOCD that has RISC-V support

mirror of svn://svn.openwrt.org/openwrt/branches/packages_10.03.1

mor1kx - an OpenRISC 1000 processor IP core

Python API wrapper around Trello's API

Wishbone Verification IP

Send a pulse from one domain to another timing domain.

GNU toolchain for RISC-V, including GCC 5.3.0

Support for Rocket Chip on Zynq FPGAs

RISC-V Proxy Kernel

Common RTL blocks used in SiFive's projects

China RISC-V User Group Website

Source files for SiFive's Freedom platforms

RISC-V Linux Port

RISC-V Cores, SoC platforms and SoCs

No description.

mirror of backfire, maybe some modify

No description.

Easily writing boring SNMP MIB with Lua.

from sf

Trac is an enhanced wiki and issue tracking system for software development projects (mirror)

git commit trello comment

odt export plugin svn clone from trac-hack

Git Plugin for Trac

No description.

暂无

An unofficial reference card for RISC-V, the free and libre ISA from UC Berkeley.

No description.

ORXSys Slides ORCONF 2015

Modernist is a Jekyll theme for GitHub Pages

Open Source Software for Developing on the Freedom E Platform

A pure Lua-based, lightweight REPL for Torch.

A Swiss army knife for your daily Linux network plumbing.

Z-scale Microarchitectural Implementation of RV32 ISA

This repo restore some files for riscv-openwrt porting.

No description.

IPython Kernel for Jupyter

Automatically exported from code.google.com/p/mtm8

Packages Repository

Application to run .travis.yml files for Python projects locally

To display Node Capture Data and Control it

A Python wrapper around the Trello API. Provides a group of Python classes to represent Trello Objects. All classes come with basic Trello API method calls and are easily extensible to suit your needs. See the README for more details.

No description.

Lua library to provide a generic socket control mechanism for large numbers of connections

Fast low-level library for BSON serialization

PyZMQ: Python bindings for zeromq

Beaker caching / session plugin for MongoDB

No description.