5-day longest streak
-
luactor
A pure Lua (at least for now) Actor Model framework.
Lua ★ 84 12y agoExplain → -
riscv-openwrt ⑂
Porting OpenWrt to RISC-V - please check https://github.com/xfguo/riscv-openwrt-port for full instructions.
C ★ 54 7y agoExplain → -
tbgen
Generate testbench for your verilog module.
Python ★ 40 8y agoExplain → -
libubox
libubox from OpenWrt.
C ★ 39 12y agoExplain → -
freescalesmartcar
飞思卡尔智能车竞赛源代码(含记忆算法)
C ★ 32 11y agoExplain → -
gitlab-commit-trello-comment
No description.
Python ★ 28 10y agoExplain → -
riscv-openwrt-port
RISC-V OpenWrt Port
Makefile ★ 17 7y agoExplain → -
spi
SPI Master Core clone from OpenCores
Verilog ★ 14 12y agoExplain → -
gpio
GPIO IP core from opencores.
Verilog ★ 12 12y agoExplain → -
wishbone_vip
Wishbone Verification IP
Verilog ★ 9 13y agoExplain → -
skyeye
skyeye git repo clone, some modify maybe
C ★ 9 14y agoExplain → -
librefpga
A libre implementation of FPGA. Written by chisel.
Scala ★ 8 8y agoExplain → -
nirgam
a clone of "nirgam", some of my modification & improvement.
C++ ★ 7 14y agoExplain → -
usbip
mirror of usbip on sf.net
C ★ 6 13y agoExplain → -
ethmac
ethmac on opencores.org
Verilog ★ 5 12y agoExplain → -
minsoc
minsoc opencores.org svn mirror
Verilog ★ 5 13y agoExplain → -
pysnmp
pysnmp with gevent adapter (developing)
Python ★ 5 13y agoExplain → -
riscv-openwrt-linux
Openwrt favorite linux kernel version. (4.1.16)
C ★ 4 10y agoExplain → -
tinyprintf
No description.
C ★ 4 12y agoExplain → -
generic_fifos
generic_fifos from OpenCores/ASICS.ws
Verilog ★ 4 12y agoExplain → -
wb_mp_mem
Wishbone Multi-Ports Memory Slave Module
Verilog ★ 4 12y agoExplain → -
ethernet_tri_mode
10/100/1000 Mbps Tri-Mode Ethernet MAC clone from OpenCores.org
Verilog ★ 3 13y agoExplain → -
jtag_tap
JTAG Test Access Port from OpenCores
Verilog ★ 3 12y agoExplain → -
adv_debug_sys
Advanced Debug System by Nathan Yawn clone from OpenCores.org
C ★ 3 10y agoExplain → -
nordb
Key-Value Database for SPI NOR Flash
C ★ 3 13y agoExplain → -
wb_memory
Wishbone Memory IP Library
Verilog ★ 3 12y agoExplain → -
wb_interconnect
Wishbone Interconnect Library
Verilog ★ 3 12y agoExplain → -
or1200
OR1200 OpenRISC processor
Verilog ★ 3 13y agoExplain → -
uart16550
No description.
Verilog ★ 3 13y agoExplain → -
lua-daemon
A Lua C-extension for daemonizing a process.
C ★ 3 13y agoExplain → -
vlsi-class-project
vlsi class project in Fudan Univ.
Python ★ 2 13y agoExplain → -
jtag_vpi ⑂
TCP/IP controlled VPI JTAG Interface.
Verilog ★ 2 12y agoExplain → -
rocket-chip ⑂
Rocket Chip Generator
Scala ★ 2 9y agoExplain → -
trello-slide ⑂
《Trello: 小团队项目管理的利器》Slide
JavaScript ★ 2 13y agoExplain → -
job-online
Submit Resume, Filling out Questionnaire.
JavaScript ★ 2 13y agoExplain → -
snmp_orm ⑂
Abstraction for pysnmp
Python ★ 2 13y agoExplain → -
chisel-template-w-rocket-chip
No description.
Scala ★ 1 7y agoExplain → -
rt-thread ⑂
RT-Thread is an open source real-time operating system for embedded devices from China.
★ 1 8y agoExplain → -
downloadsplugin
downloadsplugin for trac
Python ★ 1 13y agoExplain → -
dockutils-tp-x200
dockutils for my Thinkpad X200
Shell ★ 1 13y agoExplain → -
distro ⑂
Torch installation in a self-contained folder
CMake ★ 1 9y agoExplain → -
contiki ⑂
The official git repository for Contiki, the open source OS for the Internet of Things
C ★ 1 13y agoExplain → -
cerbero ⑂
Cerbero build system used to build the official upstream GStreamer 1.0 SDK binaries
Python ★ 1 9y agoExplain → -
asciidoctor-pdf-cjk-kai_gen_gothic ⑂
No description.
★ 1 10y agoExplain → -
menuconfig
mirror of http://code.google.com/p/menuconfig/, menuconfig is a easier way to configure your project.
C ★ 1 13y agoExplain → -
riscv-openocd ⑂
Fork of OpenOCD that has RISC-V support
C ★ 1 8y agoExplain → -
packages_10.03.1
mirror of svn://svn.openwrt.org/openwrt/branches/packages_10.03.1
C ★ 1 12y agoExplain → -
mor1kx ⑂
mor1kx - an OpenRISC 1000 processor IP core
Verilog ★ 1 12y agoExplain → -
py-trello ⑂
Python API wrapper around Trello's API
Python ★ 1 12y agoExplain → -
wb_vip
Wishbone Verification IP
Verilog ★ 1 12y agoExplain → -
xdom_pulse_sender
Send a pulse from one domain to another timing domain.
Verilog ★ 1 11y agoExplain → -
riscv-gnu-toolchain ⑂
GNU toolchain for RISC-V, including GCC 5.3.0
C ★ 1 10y agoExplain → -
fpga-zynq ⑂
Support for Rocket Chip on Zynq FPGAs
Verilog ★ 1 10y agoExplain → -
riscv-pk ⑂
RISC-V Proxy Kernel
C ★ 1 9y agoExplain → -
sifive-blocks ⑂
Common RTL blocks used in SiFive's projects
Scala ★ 1 9y agoExplain → -
home ⑂
China RISC-V User Group Website
CSS ★ 1 8y agoExplain → -
freedom ⑂
Source files for SiFive's Freedom platforms
Verilog ★ 1 8y agoExplain → -
riscv-linux ⑂
RISC-V Linux Port
C ★ 1 7y agoExplain → -
riscv-cores-list ⑂
RISC-V Cores, SoC platforms and SoCs
★ 1 6y agoExplain → -
Toy-Parallel-Mux-Generator ⑂
No description.
★ 1 5y agoExplain → -
openwrt-backfire
mirror of backfire, maybe some modify
C ★ 1 13y agoExplain → -
openOCD
No description.
C ★ 1 11y agoExplain → -
smartsnmp ⑂
Easily writing boring SNMP MIB with Lua.
C ★ 1 11y agoExplain → -
nanostack-1.x
from sf
C ★ 1 12y agoExplain → -
trac ⑂
Trac is an enhanced wiki and issue tracking system for software development projects (mirror)
Python ★ 1 14y agoExplain → -
git-commit-trello-comment
git commit trello comment
Python ★ 1 13y agoExplain → -
odtexportplugin
odt export plugin svn clone from trac-hack
Python ★ 1 14y agoExplain → -
trac-git-plugin ⑂
Git Plugin for Trac
Python ★ 1 14y agoExplain → -
scratchip-binary
No description.
★ 0 6y agoExplain → -
vpn ⑂
暂无
★ 0 7y agoExplain → -
riscv-card ⑂
An unofficial reference card for RISC-V, the free and libre ISA from UC Berkeley.
TeX ★ 0 8y agoExplain → -
risc-v-day-shanghai-2018-souvenir
No description.
★ 0 8y agoExplain → -
orxsys-slides
ORXSys Slides ORCONF 2015
HTML ★ 0 10y agoExplain → -
modernist ⑂
Modernist is a Jekyll theme for GitHub Pages
CSS ★ 0 9y agoExplain → -
freedom-e-sdk ⑂
Open Source Software for Developing on the Freedom E Platform
C ★ 0 8y agoExplain → -
trepl ⑂
A pure Lua-based, lightweight REPL for Torch.
Lua ★ 0 9y agoExplain → -
netsniff-ng ⑂
A Swiss army knife for your daily Linux network plumbing.
C ★ 0 10y agoExplain → -
zscale ⑂
Z-scale Microarchitectural Implementation of RV32 ISA
C ★ 0 10y agoExplain → -
riscv-openwrt-files
This repo restore some files for riscv-openwrt porting.
★ 0 10y agoExplain → -
riscv-liunx
No description.
C ★ 0 10y agoExplain → -
ipykernel ⑂
IPython Kernel for Jupyter
Python ★ 0 10y agoExplain → -
mtm8
Automatically exported from code.google.com/p/mtm8
★ 0 11y agoExplain → -
packages ⑂
Packages Repository
Makefile ★ 0 11y agoExplain → -
travis-solo ⑂
Application to run .travis.yml files for Python projects locally
Python ★ 0 12y agoExplain → -
Mushroom ⑂
To display Node Capture Data and Control it
Python ★ 0 12y agoExplain → -
Trolly ⑂
A Python wrapper around the Trello API. Provides a group of Python classes to represent Trello Objects. All classes come with basic Trello API method calls and are easily extensible to suit your needs. See the README for more details.
Python ★ 0 12y agoExplain → -
xfguo.github.io
No description.
Ruby ★ 0 12y agoExplain → -
ratchet ⑂
Lua library to provide a generic socket control mechanism for large numbers of connections
C ★ 0 13y agoExplain → -
libbson ⑂
Fast low-level library for BSON serialization
C ★ 0 13y agoExplain → -
pyzmq ⑂
PyZMQ: Python bindings for zeromq
Python ★ 0 13y agoExplain → -
mongodb_beaker ⑂
Beaker caching / session plugin for MongoDB
Python ★ 0 13y agoExplain → -
nmsdoc ⑂
No description.
★ 0 14y agoExplain →
No repos match these filters.