RISC-V ORG

RISC-V Instruction Set Manual

Documentation developer guide

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Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

RISC-V Opcodes

The RISC-V Architectural Certification Tests (ACTs) are a set of assembly language tests designed to certify that a design faithfully implements the RISC-V specification.

Sail RISC-V model

RISC-V Debug Specification Standard

OpenEmbedded/Yocto layer for RISC-V Architecture

RISC-V cryptography extensions standardisation work.

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

Working draft of the proposed RISC-V Bitmanipulation extension

Working Draft of the RISC-V J Extension Specification

RISC-V Architecture Profiles

Monorepo containing a machine-readable database of the RISC-V specification and artifact generation tools

RISC-V Packed SIMD Extension

PLIC Specification

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

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This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. and Unpriv. specifications at https://github.com/riscv/riscv-isa-manual

This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.

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Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores

RISC-V Security Model

RISC-V Integrated Matrix Development Repository

The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by an hart, address matching, encoding of permissions, exceptions for access violation, and support for virtualization.

This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.

A base container image populated with the dependencies to build the RISC-V Documentation.

RISC-V Worlds provides isolation in a hardware platform by constraining access to system physical addresses.

RISC-V Double Trap Fast-Track Extension

The ISA specification for the Zalasr extension.

High Assurance Cryptography

RISC-V SMBIOS Type 44 Spec

This task group will propose ISA extension(s) and non-ISA hardware and software interop interfaces to enable routine reuse and composition of a subcategory of custom extensions called composable extensions.

RISC-V Performance Events Specification

"B" extension - that represents the collection of the Zba, Zbb, and Zbs extensions

Post Quantum Cryptography

The Zabha extension provides support for byte and halfword atomic memory operations.

RISC-V Vector Matrix Extension

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Dot-Product Extension

The Timing Fences Task Group proposes an ISA extension to mitigate timing channels by partitioning shared microarchitectural states.

Zaamo / Zalrsc: A extension components

GitHub repository for the Functional Safety SIG Whitepaper Development

This repo will hold the specification for the proposed QoS ID extension being pursued on the fast-track process.

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RISC-V Specification Development Explorer

RISC-V Speculation Barrier

Define 2 new extensions to, along with Zihpm and Sscofpmf, enable event and instruction sampling with precise attribution.

Obviating Memory-Management Instructions after Marking PTEs Valid (Svvptc)

The Ssdtso is a fast-track extension adding a 'dynamic-RVTSO' mode of operation and on-demand per-hart switching between the memory models.

This repository holds the front matter pages for the RISC-V Library

Branch with Immediate (Zibi) Ratification Plan

developer.riscv.org website - currently in development

RISC-V International Guides

Trigger Delegation Fast-Track Specification

Sdtrig Effective Privilege Mode (Sdtrigepm) Fast-track ISA Extension

The RAS exception and interrupts extension (Ssrastraps) defines standard local interrupt numbers and exception-cause codes for reporting errors detected by RAS functions in the system.

RISC-V Self-hosted Trace Development Repositoty

This repository implements the Friendly Terminology for use with the in-solidarity-bot plugin.

Extension to the RISC-V Trace standards which is user-configurable to trace a hardware-filtered subset of instructions

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RISC-V Technical Committee Dashboard

RISC-V Integer Vector Absolute Difference

The intent of pending is to cleanly handle the case where action is 0, m is 0, u is 1, count is 1, and the U-mode instruction being executed causes a trap into M-mode.

RISC-V CPU Utilization Counter Extension (Sscpuutil) — fast-track ISA extension. Tracking: Jira RVS-4802.

AME repo without the UDB dependency!

The RISC-V Technical Meetings Calendar dynamically displays meeting times according to the user's time zone.

RISC-V Instruction Set Manual for Dmitry

RISC-V Memory Protection for Hypervisor