CHIPS Alliance ORG

Chisel: A Modern Hardware Design Language

Rocket Chip Generator

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Random instruction generator for RISC-V processor verification

VeeR EH1 core

Flexible Intermediate Representation for RTL

A template project for beginning new Chisel work

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

FOSS Flow For FPGA

Caliptra IP and firmware for integrated Root of Trust block

Test suite designed to check compliance with the SystemVerilog standard.

FuseSoC-based SoC for VeeR EH1 and EL2

VeeR EL2 Core

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Example designs showing different ways to use F4PGA toolchains.

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Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

RISC-V RV64GC emulator designed for RTL co-simulation

SystemVerilog synthesis tool

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Chisel/Firrtl execution engine

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Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

Advanced Interface Bus (AIB) die-to-die hardware open source

HW Design Collateral for Caliptra RoT IP

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Unit tests generator for RVV 1.0

FPGA tool performance profiling

FPGA Assembly (FASM) Parser and Generator

OmniXtend cache coherence protocol

Plugins for Yosys developed as part of the F4PGA project.

chipyard in mill :P

The specification for the FIRRTL language

Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)

Home of the Advanced Interface Bus (AIB) specification.

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Nix template for the chisel-based industrial designing flows.

Post-Quantum Cryptography IP Core (Crystals-Dilithium)

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A Scala library for Context-Dependent Environments

HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

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Verilator open-source SystemVerilog simulator and lint system

Python interface to FPGA interchange format

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AIB Generator: Analog hardware compiler for AIB PHY

Automatic SystemVerilog linting in github actions with the help of Verible

Caliptra MCU Software

Python library for working Standard Delay Format (SDF) Timing Annotation files.

SDK Firmware infrastructure, contain RTOS Abstraction Layer, demos, SweRV Processor Support Package, and more ...

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Intel Compiler for SystemC

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The Scala parser to parse riscv/riscv-opcodes generate

An RTL generator for a last-level shared inclusive TileLink cache controller

The 'missing header' for Chisel

High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs

Processor support packages

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Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards

PCB libraries and templates for rocket-chip based FPGA/ASIC designs

Tool for graphically viewing FPGA bitstream files and their connection to FASM features.

Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.

Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.

RTL blocks compatible with the Rocket Chip Generator

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The working draft to split rocket core out from rocket chip

Library to convert a FASM file into BELs importable into Vivado.

A SystemVerilog toolchain / suite, encompassing a number of open source tools for working with SystemVerilog and UVM

https://chipsalliance.github.io/guineveer/

FIRRTL grammar for tree-sitter

Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.

Governance-related CHIPS Alliance documents, guides etc.

Output of the sv-tests runs.

CHIPS Alliance Technical Advisory Council

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Repository to run extensive tests on the FPGA interchange format

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A matrix multiplication implementation via systolic array

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Coroutine Co-simulation Test Bench

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

Code-flow Integrity module to mitigate glitches and fault injections

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Mjolnir: AI Vulnerability Scanning Infrastructure

Various tools used for Caliptra's Continuous Integration flows

Collection of Routing Resources Graph (RR Graph) libraries for VPR

TextMate-compatible description of FIRRTL syntax for use with GitHub's Linguist

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How to run a Tock app on VeeR EL2 in simulation

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Working draft of the proposed RISC-V V vector extension

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USB core

Helper repo used in Synligs CI

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CHIPS Alliance Analog Working Group

CHIPS Alliance artwork

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Organization profile for CHIPS Alliance

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Presentation repository for CHIPS events

Built version of the Linux kernel, following the instructions in dromajo/run