Chun-Hao Chang

Typst template for thesis writing at National Cheng Kung University (NCKU), Tainan Taiwan

An small in-order, decoupled frontend-backend, pipeline CPU which implements RV32I_Zicsr and boots FreeRTOS.

An educational RISC-V processor design in SystemVerilog for teaching how real CPUs work, with simulation via Verilator, 58 standard test programs, a FreeRTOS demo, and instructor documentation.

PaperTalk IR is not a better prompt for slide generation; it is a compiler discipline for making LLM-generated documents inspectable, retargetable, and locally repairable.

Guides of Verilog, SystemVerilog, and SystemVerilog Assertion for Digital Designers.

從入門到進階的 Chisel HDL 指南

A 14-chapter Traditional Chinese tutorial for Chisel, the hardware description language built on Scala, taking readers from basic circuit types to building a full RISC-V chip generator.

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A comprehensive development environment for Digital IC Design with Docker Compose!

Useful IT services deployed by using Docker Compose

Implement RV32I

A simple 5-stage RISC-V pipeline processor simulator in Rust which is inspired by the course of Computer Architecture at ETH Zurich.

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AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Model Predictive Control for Quadrotor using acados

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Simulator for Hardware Architecture and Real-time Control

The source code of "Agents of Autonomy: A Systematic Study of Robotics on Modern Hardware" paper

A Benchmark Suite for Real-Time Robotics

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My personal math notes about learning Convex Optimization and Modern Control Theory.

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

A demo system for Ibex including debug support and some peripherals

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

The official repository for the gem5 computer-system architecture simulator.

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PicoRV32 - A Size-Optimized RISC-V CPU

DPI module for UART-based console interaction with Verilator simulations

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A retargetable MLIR-based machine learning compiler and runtime toolkit.

ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.

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RISC-V Proxy Kernel

Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf

My personal Helix Editor oconfiguration

Spike, a RISC-V ISA Simulator

RISC-V Open Source Supervisor Binary Interface

Basic development environment built from Docker

🦀️ Re-implement xv6-riscv in Rust

Let's write an OS which can run on RISC-V in Rust from scratch!

Packages for Typst.

Xv6 for RISC-V

5 Stage Pipeline CPU base on RV32I with a few fiexd-length SIMD instructions support

Implement RV32I

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